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PTB48510AAH资料 | |
PTB48510AAH PDF Download |
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File Size : 116 KB
Manufacturer:TI Description:After determining which clock edge to use, a start and stop bit, appended internally, frame the data bits in the register. The start bit is always high and the stop bit is always low. The start and stop bits function as the embedded clock bits in the serial stream. The Serializer transmits serialized data and clock bits (10+2 bits) from the serial data output (DO ) at 12 times the TCLK frequency. For example, if TCLK is 66 MHz, the serial rate is 66 x 12 = 792 Mega-bits-per-second. Since only 10 bits are from input data, the serial payload rate is 10 times the TCLK frequency. For instance, if TCLK = 66 MHz, the pay- load data rate is 66 x 10 = 660 Mbps. The data source provides TCLK and must be in the range of 40 MHz to 66 MHz nominal. The Serializer outputs (DO ) can drive a point-to-point con- nection or in limited multi-point or multi-drop backplanes. The outputs transmit data when the enable pin (DEN) is high, PWRDN = high, and SYNC1 and SYNC2 are low. When DEN is driven low, the Serializer output pins will enter TRI-STATE. When the Deserializer synchronizes to the Serializer, the LOCK pin is low. The Deserializer locks to the embedded |
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1PCS | 100PCS | 1K | 10K | ||
价 格 | |||||
型 号:PTB48510AAH 厂 家:TI 封 装: 批 号:07+ 数 量:1791 说 明:原装正品 |
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运 费:所有运费均有我司承担 所在地:深圳 新旧程度: |
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