 |
|||||||
|
|||||||
|
|
|||||||
|
|||||||
|
|
| SN74LVTH16646DL资料 | |
|
SN74LVTH16646DL PDF Download |
|
File Size : 116 KB
Manufacturer:TI Description:Parallel Mode Operation For latched parallel interfacing the LE line should be held low while changing attenuation state control logic P0.5 thru P16. To load data pulse LE from low to high and to low again. See Figure 1 and Table 1 on the next page for the parallel mode timing diagram and specifications. For direct parallel mode operation the LE line should be held high and the attenuation state is directly loaded when the parallel line logic changes. The truth table for parallel operation is shown in Table 2. |
|
| 相关型号 | |
| ◆ PJ-037A-SMT | |
| ◆ FZT591ATA | |
| ◆ 2-520081-2 | |
| ◆ 2-520103-2 | |
| ◆ G3VM21GR | |
| ◆ B40B-XADSS-N(LF)(SN) | |
| ◆ S301T-RO | |
| ◆ 172339-1 | |
| ◆ V7-5F17D8-336 | |
| ◆ 44441-2002 | |
| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
|
型 号：SN74LVTH16646DL 厂 家：TI 封 装： 批 号：07+ 数 量：28492 说 明：原装正品 |
|||||
|
运 费：所有运费均有我司承担 所在地：深圳 新旧程度： |
|||||
| 联系人：申小姐 |
| 电 话：0755-83330991,0755-83047629 |
| 手 机：15811820920 |
| QQ：2355514181 |
| MSN：chipstech-int@hotmail.com |
| 传 真：0755-61658118 |
| EMail：sales@chipstech-int.com |
| 公司地址： 深圳市福田区中航路鼎城国际1017 |
|
1. 所有我司提供的货物，均为原厂原装正品！ 2. 我们的报价是不含税价格。含税需要增加相应的税点。
|
建议使用分辨率:1024*768