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| THS3201DBVT资料 | |
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THS3201DBVT PDF Download |
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File Size : 116 KB
Manufacturer:TI Description:PCI Bus Command/Byte Enable: The command signaling and byte enables are multiplexed on the same pins. During the address phase of a transaction, C/BE[3:0]# are interpreted as the bus commands.During the data phase, C/BE[3:0]# are interpreted as byte enables. The byte enables are to be valid for the entirety of each data phase, and they indicate which bytes in the 32-bit data path are to carry meaningful data for the current data phase. Cycle Frame: This input indicates to the THS3201DBVT that a bus transaction is beginning. While FRAME# is asserted, data transfers continue. When FRAME# is de-asserted, the transaction is in its final phases. Initiator Ready: This input indicates the initiating agents ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#. Target Ready:This output indicates target Agents the THS3201DBVTs ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. Stop: This output indicates the current target is requesting the master to stop the current transaction. Initialization Device Select: This input is used as a chip select during configuration read and write transactions. This is a point-to-point signal. IDSEL can be used as a chip select during configuration read and write transactions. Device Select: This output is driven active LOW when the PCI address is recognized as supported, thereby acting as the target for the current PCI cycle. The Target must respond before timeout occurs or the cycle will terminate. Parity Error: The output is driven active LOW when a data parity error is detected during a write phase. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：THS3201DBVT 厂 家：TI 封 装： 批 号：07+ 数 量：35984 说 明：原装正品 |
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