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| THS4141IDGNR资料 | |
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THS4141IDGNR PDF Download |
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File Size : 116 KB
Manufacturer:TI Description:The CY7C1353F is a synchronous flow-through burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133-MHz device). |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：THS4141IDGNR 厂 家：TI 封 装： 批 号：07+ 数 量：27732 说 明：原装正品 |
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运 费：所有运费均有我司承担 所在地：深圳 新旧程度： |
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| 联系人：申小姐 |
| 电 话：0755-83330991,0755-83047629 |
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| 公司地址： 深圳市福田区中航路鼎城国际1017 |
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1. 所有我司提供的货物，均为原厂原装正品！ 2. 我们的报价是不含税价格。含税需要增加相应的税点。
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