 |
|||||||
|
|||||||
|
|
|||||||
|
|||||||
|
|
| TLC252CD资料 | |
|
TLC252CD PDF Download |
|
File Size : 116 KB
Manufacturer:TI Description:All voltages are referenced to VSS. Offset specified after auto-calibration cycle and Current Offset Bias register (COBR) set to 00h. To properly enter sleep mode, SMOD=1, and the application should hold SDA and SCL low for longer than the maximum tSLEEP. NBEN = 0, Current Offset Bias Register (COBR) set to 00h, and Accumulation Bias Register (ABR) set to 00h. Parameters guaranteed by design. Timing must be fast enough to prevent the DS2745 from entering sleep mode due to SDA,SCL low for period > tSLEEP. fSCL must meet the minimum clock low time plus the rise/fall times. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW ) of the SCL signal. This device internally provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant. CB¾total capacitance of one bus line in pF. The first voltage measurement after writing the ACR or after device POR is not valid. |
|
| 相关型号 | |
| ◆ PJ-037A-SMT | |
| ◆ FZT591ATA | |
| ◆ 2-520081-2 | |
| ◆ 2-520103-2 | |
| ◆ G3VM21GR | |
| ◆ B40B-XADSS-N(LF)(SN) | |
| ◆ S301T-RO | |
| ◆ 172339-1 | |
| ◆ V7-5F17D8-336 | |
| ◆ 44441-2002 | |
| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
|
型 号：TLC252CD 厂 家：TI 封 装： 批 号：07+ 数 量：36521 说 明：原装正品 |
|||||
|
运 费：所有运费均有我司承担 所在地：深圳 新旧程度： |
|||||
| 联系人：申小姐 |
| 电 话：0755-83330991,0755-83047629 |
| 手 机：15811820920 |
| QQ：2355514181 |
| MSN：chipstech-int@hotmail.com |
| 传 真：0755-61658118 |
| EMail：sales@chipstech-int.com |
| 公司地址： 深圳市福田区中航路鼎城国际1017 |
|
1. 所有我司提供的货物，均为原厂原装正品！ 2. 我们的报价是不含税价格。含税需要增加相应的税点。
|
