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| TLC542CDWR资料 | |
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TLC542CDWR PDF Download |
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File Size : 116 KB
Manufacturer:TI Description:The CPU core can use on-chip rather than external memory. This eliminates the need for large and com- plex bus interface units. Most instructions are 16 bits, so all basic instructions are just two bytes long. Additional bytes are sometimes required for immediate values, so instructions can be two or four bytes long. Non-aligned word access is allowed. Each instruction can operate on 8-bit or 16-bit data. The device is designed to operate with a clock rate in the 10 to 24 MHz range rather than 100 MHz or more. Most embedded systems face EMI and noise con- straints that limit clock speed to these lower ranges. A lower clock speed means a simpler, less costly silicon implementation. The instruction pipeline uses three stages. A smaller pipeline eliminates the need for costly branch predic- tion mechanisms and bypass registers, while maintain- ing adequate performance for typical embedded controller applications. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：TLC542CDWR 厂 家：TI 封 装： 批 号：07+ 数 量：10352 说 明：原装正品 |
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运 费：所有运费均有我司承担 所在地：深圳 新旧程度： |
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| 联系人：申小姐 |
| 电 话：0755-83330991,0755-83047629 |
| 手 机：15811820920 |
| QQ：2355514181 |
| MSN：chipstech-int@hotmail.com |
| 传 真：0755-61658118 |
| EMail：sales@chipstech-int.com |
| 公司地址： 深圳市福田区中航路鼎城国际1017 |
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1. 所有我司提供的货物，均为原厂原装正品！ 2. 我们的报价是不含税价格。含税需要增加相应的税点。
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