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| TLE2024AIDW资料 | |
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TLE2024AIDW PDF Download |
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File Size : 116 KB
Manufacturer:TI Description:The TLE2024AIDW is 4,718,592 bits Synchronous Static Ran- dom Access Memory designed to support zero wait state per- formance for advanced Pentium/Power PC based system. And with CS1 high, ADSP is blocked to control signals. It can be organized as 128K words of 36 bits. And it integrates address and control registers, a 2-bit burst address counter and high output drive circuitry onto a single integrated circuit for reduced components counts implementation of high perfor- mance cache RAM applications. Write cycles are internally self-timed and synchronous. The self-timed write feature eliminates complex off chip write pulse shaping logic, simplifying the cache design and further reducing the component count. Burst cycle can be initiated with either the address status pro- cessor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the systems burst sequence and are controlled by the burst address advance(ADV) input. ZZ pin controls Power Down State and reduces Stand-by cur- rent regardless of CLK. The TLE2024AIDW is implemented with SAMSUNGs high per- formance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to mini- mize ground bounce. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：TLE2024AIDW 厂 家：TI 封 装： 批 号：07+ 数 量：37169 说 明：原装正品 |
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运 费：所有运费均有我司承担 所在地：深圳 新旧程度： |
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| 联系人：申小姐 |
| 电 话：0755-83330991,0755-83047629 |
| 手 机：15811820920 |
| QQ：2355514181 |
| MSN：chipstech-int@hotmail.com |
| 传 真：0755-61658118 |
| EMail：sales@chipstech-int.com |
| 公司地址： 深圳市福田区中航路鼎城国际1017 |
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1. 所有我司提供的货物，均为原厂原装正品！ 2. 我们的报价是不含税价格。含税需要增加相应的税点。
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