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| TLV2444IDR资料 | |
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TLV2444IDR PDF Download |
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File Size : 116 KB
Manufacturer:TI Description:not WCLK. Similarly the PAF is asserted and updated on the rising edge of WCLK only and not RCLK. This device includes a Retransmit from Mark feature that utilizes two control inputs, MARK and RT (Retransmit). If the MARK input is enabled with respect to the RCLK, the memory location being read at the point will be marked. Any subsequent retransmit operation (when RT goes LOW), will reset the read pointer to this marked location. The device can be configured with different input and output bus widths as previously stated. These rates are: x40 to x40, x40 to x20,x40 to x10, x20 to x40, and x10 to x40. If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state. A JTAG test port is provided, here the FIFO has fully functional boundary Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and Boundary Scan Architecture. The Double Data Rate FIFO has the capability of operating in either LVTTL or HSTL mode. HSTL mode can be selected by enabling the HSTL pin. Both input and output ports will operate in either HSTL or LVTTL mode, but cannot be selected independent of one another. The IDT72T4088/72T4098/72T40108/72T40118 are fabricated using IDTs high-speed submicron CMOS technology. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：TLV2444IDR 厂 家：TI 封 装： 批 号：07+ 数 量：30856 说 明：原装正品 |
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运 费：所有运费均有我司承担 所在地：深圳 新旧程度： |
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| 联系人：申小姐 |
| 电 话：0755-83330991,0755-83047629 |
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| 公司地址： 深圳市福田区中航路鼎城国际1017 |
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1. 所有我司提供的货物，均为原厂原装正品！ 2. 我们的报价是不含税价格。含税需要增加相应的税点。
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