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| TLV2461CDBVR资料 | |
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TLV2461CDBVR PDF Download |
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File Size : 116 KB
Manufacturer:TI Description:In order to specify each device for true worst case operat- ing conditions all timing parameters are guaranteed while the chip is driving the capacitive load of 88 DRAMs includ- ing trace capacitance The chips delay timing logic makes use of a patented new delay line technique which keeps A C skew to g3 ns over the full VCC range of g10% and temperature range of b55 C to a 125 C The DP8417 DP8418 DP8419 and DP8419X guarantee a maximum RASIN to CASOUT delay of 80 ns or 70 ns even while driv- ing a 2 Mbyte memory array with error correction check bits included Speed selected options of these devices are shown in the switching characteristics section of this docu- ment With its four independent RAS outputs and nine multiplexed address outputs the DP8419 can support up to four banks of 16k 64k or 256k DRAMs Two bank select pins B1 and B0 are decoded to activate one of the RAS signals during |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：TLV2461CDBVR 厂 家：TI 封 装： 批 号：07+ 数 量：52179 说 明：原装正品 |
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运 费：所有运费均有我司承担 所在地：深圳 新旧程度： |
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| 联系人：申小姐 |
| 电 话：0755-83330991,0755-83047629 |
| 手 机：15811820920 |
| QQ：2355514181 |
| MSN：chipstech-int@hotmail.com |
| 传 真：0755-61658118 |
| EMail：sales@chipstech-int.com |
| 公司地址： 深圳市福田区中航路鼎城国际1017 |
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1. 所有我司提供的货物，均为原厂原装正品！ 2. 我们的报价是不含税价格。含税需要增加相应的税点。
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