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| TLV2760CDG4资料 | |
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TLV2760CDG4 PDF Download |
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File Size : 116 KB
Manufacturer:TI Description:Parameter MASTER CLOCK (CLI) (See Figure 16) CLI Clock Period CLI High/Low Pulse Width Delay from CLI to Internal Pixel Period Position CLPOB PULSE WIDTH (PROGRAMMABLE)1 SAMPLE CLOCKS (See Figure 18) SHP Rising Edge to SHD Rising Edge DATA OUTPUTS (See Figure 19 and Figure 20) Output Delay From Programmed Edge Pipeline Delay SERIAL INTERFACE (SERIAL TIMING SHOWN IN Figure 14 and Figure 15) Maximum SCK Frequency SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold SCK Falling Edge to SDATA Valid Read |
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| ◆ 44441-2002 | |
| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：TLV2760CDG4 厂 家：TI 封 装： 批 号：07+ 数 量：7119 说 明：原装正品 |
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运 费：所有运费均有我司承担 所在地：深圳 新旧程度： |
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| 联系人：申小姐 |
| 电 话：0755-83330991,0755-83047629 |
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| 公司地址： 深圳市福田区中航路鼎城国际1017 |
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1. 所有我司提供的货物，均为原厂原装正品！ 2. 我们的报价是不含税价格。含税需要增加相应的税点。
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