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| TLV2760IP资料 | |
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TLV2760IP PDF Download |
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File Size : 116 KB
Manufacturer:TI Description:Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write op- erations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G). The Output Enable, G, con- trols the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memorys Com- mand Interface. Reset/Block Temporary Unprotect (RP). The Re- set/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to tem- porarily unprotect all blocks that have been pro- tected. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, V IH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 14 and Figure 10, Reset/ Temporary Unprotect AC Characteristics for more details. Holding RP at V ID will temporarily unprotect the protected blocks in the memory. Program and Erase operations on all blocks will be possible. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：TLV2760IP 厂 家：TI 封 装： 批 号：07+ 数 量：30677 说 明：原装正品 |
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运 费：所有运费均有我司承担 所在地：深圳 新旧程度： |
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1. 所有我司提供的货物，均为原厂原装正品！ 2. 我们的报价是不含税价格。含税需要增加相应的税点。
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