 |
|||||||
|
|||||||
|
|
|||||||
|
|||||||
|
|
| TPA6205A1ZQVR资料 | |
|
TPA6205A1ZQVR PDF Download |
|
File Size : 116 KB
Manufacturer:TI Description: The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst se- quence. The 256Mb SDRAM uses an internal pipelined ar- chitecture to achieve high-speed operation. This ar- chitecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high- speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high- speed, random-access operation. The 256Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All in- puts and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM oper- ating performance, including the ability to synchro- nously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. |
|
| 相关型号 | |
| ◆ PJ-037A-SMT | |
| ◆ FZT591ATA | |
| ◆ 2-520081-2 | |
| ◆ 2-520103-2 | |
| ◆ G3VM21GR | |
| ◆ B40B-XADSS-N(LF)(SN) | |
| ◆ S301T-RO | |
| ◆ 172339-1 | |
| ◆ V7-5F17D8-336 | |
| ◆ 44441-2002 | |
| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
|
型 号：TPA6205A1ZQVR 厂 家：TI 封 装： 批 号：07+ 数 量：20377 说 明：原装正品 |
|||||
|
运 费：所有运费均有我司承担 所在地：深圳 新旧程度： |
|||||
| 联系人：申小姐 |
| 电 话：0755-83330991,0755-83047629 |
| 手 机：15811820920 |
| QQ：2355514181 |
| MSN：chipstech-int@hotmail.com |
| 传 真：0755-61658118 |
| EMail：sales@chipstech-int.com |
| 公司地址： 深圳市福田区中航路鼎城国际1017 |
|
1. 所有我司提供的货物，均为原厂原装正品！ 2. 我们的报价是不含税价格。含税需要增加相应的税点。
|
建议使用分辨率:1024*768