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| TPS61140DRCT资料 | |
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TPS61140DRCT PDF Download |
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File Size : 116 KB
Manufacturer:TI Description:2.2 Initialization procedure After VCC has stabilized, the device will be in the transmit-only mode. Nine clock cycles on the VCLK pin must be given to the device for it to perform internal synchronization. During this period, the SDA pin will be in a high impedance state. On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the most significant bit of a byte. The device will power up at an indeterminate byte address. (Figure 2-2). |
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| ◆ 44441-2002 | |
| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：TPS61140DRCT 厂 家：TI 封 装： 批 号：07+ 数 量：8858 说 明：原装正品 |
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运 费：所有运费均有我司承担 所在地：深圳 新旧程度： |
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